1. Field of the Invention
The present invention relates to microprocessor programmable architectures, and particularly to a multi-cycle programmable processor.
2. Description of the Related Art
A microprocessor is the core of all computing devices. It is a programmable, clock-driven, and register-based device that collects data from a source, figures out the information, performs calculations, and at the end, produces the desired results. The final results can then be output to an output peripheral device or stored in local or external memory. Processors are created from integrated circuits (IC) that incorporate most or all of the functions of a central processing unit (CPU) that is needed in any computing device. Processors are nowadays used in almost all electrical and electronics equipment.
Embedded systems rely on special purpose digital processors to perform their specialized task. In the realm of real-time signal processing and mobile embedded systems, clock delays and the corresponding power dissipation associated with longer clock periods are becoming the bottlenecks for such systems and are slowing them down from performing quick real-time computations.
To overcome this bottleneck, multi-cycle operation within processors was introduced. The time period of a clock can be significantly reduced in this implementation compared to single cycle implementation, which, in turn, will speed up the processing time. Such an implementation restricts each clock cycle to use only one major functional unit, while at the end of every clock cycle the intermediate results are stored in ‘internal’ registers for use in later cycles.
Multi-cycle operation signifies that each instruction in the processors will take several clock cycles to execute. The basic idea is to break down the long cycle into multiple shorter cycles. The time period of a clock can be significantly reduced in comparison with single cycle implementation, which, in turn, will speed up the processing time. In addition, a multiple-cycle implementation restricts each clock cycle to use only one major functional unit. At the end of every clock cycle, the intermediate results are stored in ‘internal’ registers for use in later cycles.
Generally speaking, a microprocessor executes each of its instructions in an instruction fetch stage, an instruction decode stage, an execute stage, a memory access stage, and a write-back stage, each stage being executable in one clock cycle of the microprocessor to provide for a 5-cycles per instruction throughput. The typical MIPS processor utilizes a computer architecture that allows for pipelining without interlocking stages to improve performance over the aforementioned 5-cycle per instruction. This performance improvement varies according to instruction type.
For example, a typical MIPS microprocessor executes a Load instruction in 5 cycles, a Store instruction in 4 cycles, an R-type instruction in 4 cycles, a Branch instruction in 3 cycles, and a Jump instruction in 3 cycles. Thus, the performance improvement is based on the mix of instruction types found in the computer application at hand. As the mix of instructions varies considerably based upon the type of processing application being run, it would be desirable to de-couple the performance improvement from the mix of instructions in the program being executed.
Thus, a multi-cycle programmable processor solving the aforementioned problems is desired.